1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits, and, more particularly, to integrated circuits wherein a diffusion barrier layer is employed for substantially avoiding or at least reducing a diffusion of an electrically conductive material.
2. Description of the Related Art
Integrated circuits include a number of individual circuit elements, such as, for example, transistors, capacitors, diodes and resistors, which are interconnected by means of electrically conductive lines. The electrically conductive lines may be formed of an electrically conductive material including copper, such as substantially pure copper or a copper alloy, for example, an alloy of copper and aluminum. For forming the electrically conductive lines, damascene techniques may be employed.
In damascene techniques, trenches and contact vias are formed in an interlayer dielectric, which may include silicon dioxide and/or a low-k material having a smaller dielectric constant than silicon dioxide. In the trenches and contact vias, a diffusion barrier layer may be formed. After the formation of the diffusion barrier layer, the trenches and contact vias may be filled with the electrically conductive material including copper. This may be done by means of electroplating for depositing the electrically conductive material and chemical mechanical polishing for removing portions of the electrically conductive material deposited outside the trenches and contact vias.
The diffusion barrier layer may help to substantially avoid or at least reduce a diffusion of copper from the electrically conductive material into the interlayer dielectric and/or other portions of the semiconductor structure, which might adversely affect the functionality of the integrated circuit.
Issues that can occur in the above-described damascene process may include a formation of defects in the diffusion barrier layer, such as pores and/or cracks. Defects in the diffusion barrier layer may allow an undesirable diffusion of copper from the electrically conductive material into the interlayer dielectric and/or other portions of the semiconductor structure. Additionally, defects of the diffusion barrier layer may induce an insufficient filling of contact vias and/or trenches, such that voids are created in the electrically conductive material. Such voids may increase the electrical resistance of electrically conductive lines, and the presence of voids may increase the likelihood of electromigration and/or stress migration occurring. In the operation of an integrated circuit having a diffusion barrier layer including defects, the defects in the diffusion barrier layer may lead to an increased diffusion of copper due to electromigration and/or stress migration. A formation of voids within electrically conductive lines may be a severe reliability risk.
Therefore, methods for testing the integrity of a diffusion barrier layer may be employed in the manufacturing of integrated circuits for developing methods of forming a diffusion barrier layer which substantially eliminate or at least reduce the likelihood of the formation of defects in the diffusion barrier layer and/or for monitoring processes employed for forming a diffusion barrier layer in the manufacturing of integrated circuits.
U.S. Publication No. 2008/0160654 discloses exposing a semiconductor structure, including an electrically conductive feature formed of a first material including copper and a diffusion barrier layer formed on the electrically conductive feature and including a second material, to an etchant adapted to selectively remove the first material, leaving the second material substantially intact. The etchant may include, for example, ammonium peroxydisulfate.
If the diffusion barrier layer including the second material has defects, such as, for example, pores, the etchant can contact the first material in the electrically conductive feature. Thus, the electrically conductive feature is affected by the etchant, which may lead to the formation of a cavity in the electrically conductive feature. Conversely, if the diffusion barrier layer is intact and does not include defects, the diffusion barrier layer can prevent a contact between the etchant and the first material in the electrically conductive feature below the diffusion barrier layer. Thus, the electrically conductive feature is protected from being affected by the etchant, and no cavity is formed.
The presence of cavities in the electrically conductive feature can then be detected by means of techniques of microscopy, wherein the presence of cavities indicates the occurrence of defects in the diffusion barrier layer.
Other techniques for testing the integrity of diffusion barrier layers may include an HF dip, wherein a semiconductor structure is exposed to hydrofluoric acid (HF) after the deposition of a diffusion barrier layer on an interlayer dielectric. If there are defects in the diffusion barrier layer, the interlayer dielectric is affected by the hydrofluoric acid, which can be detected by means of techniques of microscopy. Further techniques for testing the integrity of a diffusion barrier layer may include inline electrical barrier measurements on trenches filled with an electrically conductive material, Kelvin vias and via chains. In these techniques, defects are detected by electrical measurements on electrically conductive features in semiconductor structures including an electrically conductive material and diffusion barrier layers.
The above-described techniques for detecting defects in diffusion barrier layers may have issues associated therewith. Techniques such as those described in U.S. Publication No. 2008/0160654 or the HF dip are associated with a destruction of portions of the semiconductor structure adjacent the diffusion barrier layer, such as the electrically conductive material of the electrically conductive line and/or the interlayer dielectric. Electrical barrier measurements may have a limited sensitivity with respect to small defects.
In view of the situation described above, the present disclosure provides methods wherein some or all of the above-mentioned issues may be substantially avoided or at least reduced.